Altera ALTDLL - Manual (Page 61)

4–25 Chapter 4: Functional Description
DQS_CONFIG / IO_CONFIG Block
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
Setting the Input Delay Chain to 50 ps Delay
In Figure 4–20 , cursor 3 (255 ns) to cursor 4 (1355 ns) show that the delay chain is
configured to 50 ps.
The config_clock takes 11 (1,100 ns) clock cycles to load the intended delay values
into the IO_CONFIG block because of the first four clock cycles (for the input delay
chain, D1), the next three clock cycles (for the output delay chain 2, D6) and the last 4
clock cycles (for the output delay chain 1, D5).
The following steps describe how the input delay chain changes:
1. Because there is a 11-bit shift register in the IO_CONFIG block,
bidir_core_dq_confiq_enable(0) is asserted for 11 clock cycles. When the
shift registers are fully loaded, the shift registers have their bits arranges to
correspond with datain values.
2. The config_datain signal is asserted at the 4th clock cycle to change the input
delay chain value.
3. The delay only takes effect when the config_update signal is asserted for one
clock cycle at 1455,000 ps (Cursor 5).
4. After the config_update signal is deasserted, the delay from
bidir_dq_0_input_delay_chain_inst/datain at 1630,000 ps (Cursor 7) to
bidir_dq_0_input_delay_chain_inst/dataout at 1630,050 ps (Cursor 8)
is noticeable, which is 50 ps. Refer to Figure 4–21 .