Altera ALTDLL - Manual (Page 70)

Chapter 4: Functional Description 4–34
ALTDQ_DQS Megafunction Ports
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
dqs_enable_in Input Optional V
CC
This active-high port is connected to the
DQS_ENABLE:dqsenable that is used to enable or
disable the DQS_ENABLE:dqsbusout port. When
the dqs_enable_in port is connected to GND, the
DQS_ENABLE:dqsbusout signal is GND on the
next falling edge of the DQS_ENABLE:dqsin signal.
The DQS_ENABLE:dqsbusout is connected
directly to the dqs_bus_out port.
dqs_input_data_in Input Optional GND This port receives the incoming DQS signal for the DQS
input path
dqs_input_data_out Output Optional — This port receives the outgoing DQS signal from the
DQS_INPUT_DELAY_CHAIN:busout port, or
directly from the dqs_input_data_in port
dqsupdateen Input Optional GND This active-high port is connected to the
DQS_DELAY_CHAIN:dqsupdateen port that is
used to latch the
DQS_DELAY_CHAIN:delayctrlin[5..0] and
DQS_DELAY_CHAIN:offsetctrlin[5..0]
signals. The dqsupdateen port is fed by the
ALTDLL:dll_dqsupdate port, or the core.
Io_clock_divider_clk Input Optional GND This port is connected to the
IO_CLOCK_DIVIDER:clk port that is the clock
input port for that block.
Io_clock_divider_
clkout[n
c
-1..0]
Output Optional — This port is connected to the
IO_CLOCK_DIVIDER:clkout port that is used to
output clock signal that is half the frequency of the
IO_CLOCK_DIVIDER:clk signal.
Io_clock_divider_
masterin
Input Optional GND This port is connected to the
IO_CLOCK_DIVIDER : masterin port that is used
when you need to chain multiple clock dividers together
to feed wider DQS groups.
Io_clock_divider_
slaveout
Output Optional — This port is connected to the
IO_CLOCK_DIVIDER:slaveout port that is used
when you need to chain multiple clock dividers together
to feed wider DQS groups. This port must not have
more than one fan-out and must only be connected to
the
io_clock_divider_masterin port of
another ALTDQ_DQS megafunction.
offsetctrlin[5..0] Input Optional GND This port receives the Gray-coded fine-tune delay chain
setting for the DQS output path from the
ALTDLL:dll_offset_ctrl_a_offsetctrlo
ut[5..0] port or
ALTDLL:dll_offset_ctrl_b_offsetctrlo
ut[5..0] . This port must match the polarity of its
source and cannot be inverted.
Table 4–11. Megafunction Ports to Configure DQS Input Path (Part 2 of 2)
Port Name Type
Optional/
Required
Default Description