Altera ALTDLL - Manual (Page 89)

4–53 Chapter 4: Functional Description
Design Example: Implementing Half-Rate DDR2 Interface in Stratix III
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
8. On the DQ OUT/OE page, specify the parameters as shown in Table 4–30 . These
parameters configure the DQ OUTPUT and DQ OE path of the ALTDQ_DQS
instance.
9. On the Half-rate page, specify the parameters as shown in Table 4–31 . These
parameters configure the half-rate settings of the ALTDQ_DQS instance.
10. On the DQSn I/O page, specify the parameters as shown in Table 4–32 . .
11. On the Reset/Config Ports page, specify the parameters as shown in Table 4–33 .
Use DQ half rate ‘dataoutbypass’ port — Turned off
Use DQ input delay chain — Turned on
Table 4–30. Advance Options (DQ OUT/OE)
Parameter Value
Enable DQ output delay chain1 Turned on
Enable DQ output delay chain2 Turned on
DQ output register mode DDIO
Enable DQ output enable Turned on
Enable DQ output enable delay chain1 Turned on
Enable DQ output enable delay chain2 Turned on
DQ output enable register mode DDIO
Table 4–31. Advance Options (Half-Rate)
Parameter Value
IO Clock Divider Source Core
Create ‘io_clock_divider_masterin’ input port Turned off
Create ‘io_clock_divider_clkout’ output port Turned on
Create ‘io_clock_divider_slaveout’ output port Turned off
IO Clock Divider Invert Phase Never
Table 4–32. Advanced Options (DQS/DQSn IO)
Parameter Value
Use DQSn IO Turned on
DQS and DQSn IO Configuration mode Differential Pair
Table 4–33. Advanced Options (Reset and Config Ports) (Part 1 of 2)
Parameter Value
Create ‘dqs_areset’ input port Turned on
Create ‘dqs_sreset’ input port Turned on
Create ‘input_dq_areset’ input port Turned off
Create ‘input_dq_sreset’ input port Turned off
Create ‘output_dq_areset’ input port Turned off
Table 4–29. Advance Options (DQ IN) (Part 2 of 2)
Parameter Sub-options Value