Altera ALTDLL - Manual (Page 78)

Chapter 4: Functional Description 4–42
ALTDQ_DQS Megafunction Ports
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
DQ OE Path Megafunction Ports
Table 4–17 summarizes all the ports on the megafunction that configure the DQ OE
path. The possible values for are BIDIR_DQ and OUTPUT_DQ .
Table 4–17. Megafunction Ports to Configure DQ OE Path (Part 1 of 2)
Port Name Type
Optional/
Required Default Description
bidir_dq_areset
[n
b
-1..0]
Input Optional GND This port is connected to all areset port in the
bidir DQ IO primitives that is used to
asynchronously reset the registers in those
primitives.
bidir_dq_hr_oe_in
[2*n
b
-1..0]
Input Optional GND This port feeds the half-rate bidirectional DQ OE
signal for the
BIDIR_DQ_OE_HR_DDIO_OUT:datainhi /
datainlo ports.
bidir_dq_oe_in
[n
b
-1..0]
Input Optional GND This port feeds the bidirectional DQ OE signal for
the
BIDIR_DQ_OE_FF:d ,
BIDIR_DQ_OE_DDIO_OE:oe ,
BIDIR_DQ_OE_DELAY_CHAIN1:datain ,
BIDIR_DQ_OE_DELAY_CHAIN2:datain ,
or bidir_dq_oe_out port.
bidir_dq_oe_out
[n
b
-1..0]
Output Optional — This port is driven by the
BIDIR_DQ_OE_DELAY_CHAIN2:dataout ,
BIDIR_DQ_OE_DELAY_CHAIN1:dataout ,
BIDIR_DQ_OE_FF:q ,
BIDIR_DQ_OE_DDIO_OE:dataout , or
bidir_dq_oe_in port.
bidir_dq_sreset
[n
b
-1..0]
Input Optional GND This port is connected to all sreset port in the
bidir DQ IO primitives that is used to
synchronously reset the registers in those
primitives.
dq_hr_output_reg_clk Input Optional GND This port feeds the half-rate clock signal for the
_OE_HR_DDIO_OUT:clkhi / clklo /
muxsel ports. The clock signal is for the half-rate
DDIO registers.
dq_output_reg_clk Input Optional GND This port feeds the clock signal for the
_OE_FF:clk and
_OE_DDIO_OE:clk ports.
dq_output_reg_clkena Input Optional V
CC
This port feeds the output enable signal for the
_OE_FF:ena and
_OE_DDIO_OE:ena ports.
output_dq_areset
[n
o
-1..0]
Input Optional GND This port is connected to all areset ports in the
output DQ IO primitives that is used to
asynchronously reset the registers in those
primitives.
output_dq_hr_oe_in
[2* n
o
-1..0]
Input Optional GND This port feeds the half-rate output DQ OE signal
for the
OUTPUT_DQ_OE_HR_DDIO_OUT:datainhi
/ datainlo ports.