Altera ALTDLL - Manual (Page 96)

Chapter 4: Functional Description 4–60
Design Example: Implementing Half-Rate DDR2 Interface in Stratix III Devices
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
Understanding the Simulation Results
This section describes the simulation results of “Design Example: Implementing
Half-Rate DDR2 Interface in Stratix III Devices” on page 4–49 .
Writing Data to the External Memory
The following sequence describes the transferring of data from the FPGA core to the
bidirectional DQ pins with various delay chain settings (refer to
Figure 4–25 on
page 4–63 ):
1. The simulation begins when the PLL is locked, as indicated by the assertion of the
locked signal at 225,000 ps (refer to Figure 4–25 ). At this point, the PLL input
frequency, as indicated by the inclk0 signal, is 200 MHz.
2. The c0 , c1 , and c2 ports generate a 333.333-MHz clock output while the c3 port
generates a 166.666-MHz clock output.
1 This design example uses the half-rate option, which means that the FPGA
core sends and receives data from the external memory interface at a
half-rate of 166.666 MHz. The pin that interfaces with the memory toggles
at 333.333 MHz. However, because this pin is also toggled by a
DDIO_OUT
signal, the data throughput is 666.666 Mbps.
3. The output path from the FPGA core to the bidirectional DQ pin is represented by
a 32-bit input, bidir_dq_hr_output_data_in [31:0] . The input path from
the bidirectional pin to the FPGA core is represented by a 32-bit output,
bidir_dq_hr_input_data_out[31:0] . The OE path from the FPGA core to
the bidirectional buffer, bidir_dq_hr_oe_in[15:0] , is 16 bits wide and is
active-low.
4. For the DQ output pin, the output path in the FPGA core to the bidirectional DQ
pin is represented by a 4-bit input, output_dq_hr_output_data_in [3:0] .
The OE path is 2 bits wide from the FPGA core to the bidirectional buffer,
output_dq_hr_oe_in[1:0] .
1 In the first part of the simulation, only output paths are used; therefore,
bidir_dq_hr_oe_in[15:0] = 16’b0 and dqs_hr_oe_in [1:0] =
2’b0.
5. For bidir_dq_hr_output_data_in[31:0] , each bit is toggled with a 10-MHz
data signal from 100 ns to 300 ns. The toggling behavior of
bidir_dq_hr_output_data_in[31:0] is represented in the waveform in
groups of 4-bit signals (for example, bidir_dq_hr_output_data_in[3:0] ),
as the four input paths are connected to the bidir_dq_io[0] pin.
6. The bidir_dq_hr_output_data_in[3] and
bidir_dq_hr_output_data_in[2] signals go through the DDIO_OUT port,
which is clocked at 166.666 MHz by the c3 PLL clock output. At the same time, the
bidir_dq_hr_output_data_in[1] and
bidir_dq_hr_output_data_in[0] signals go through another DDIO_OUT
port, which is clocked at 166.666 MHz by the c3 PLL clock output.