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Altera ALTDLL User Manual

Page 15

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2–9

Chapter 2: Getting Started

Design Example: Implementing Read Paths Using Stratix III Devices

ALTDLL and ALTDQ_DQS Megafunctions User Guide

© February 2012

Altera Corporation

7. On the DQS OUT/OE page, turn off the Enable DQS output path option. When

you deselect the Enable DQS output path option, the other options on this page
are disabled.

8. On the DQ IN page, specify the parameters as shown in

Table 2–7

. These

parameters configure the DQ input path of the ALTDQ_DQS instance.

9. On the DQ OUT/OE page, all the options are automatically disabled because the

design is not using output DQ. The parameters on this page configure the DQ
output and OE paths of the ALTDQ_DQS instance.

10. On the Half-rate page, for the IO Clock Divider Invert Phase parameter, turn on

Never

because the design requires full-rate components. The other options are

automatically disabled. The parameters on this page configure the half-rate
settings of the ALTDQ_DQS instance.

11. On the OCT Path page, all the options are automatically disabled because the

design is not using input and output DQS or bidirectional DQ. The parameters on
this page configure the OCT path of the ALTDQ_DQS instance.

12. On the DQSn I/O page, turn off the Use DQSn I/O option because the design is

not using DQSn. When you turn off the Use DQSn I/O option, the other options
on this page are disabled.

13. In the Reset/Config Ports tab, tun off all the parameters.

14. Click Finish.

15. Click Finish. The ALTDQ_DQS instance is generated.

16. Click OK to close the Symbol window.

17. Place the instance on the Block Editor.

Enable DQS busout delay chain

Turned on.

Enable DQS enable block

Turned on.

Table 2–7. Advance Options (DQ IN)

Options

Value

DQ input register mode

DDIO

Select DDIO to enable double data rate capture for
DQ.

DQ input register clock source

dqs_bus_out port and turn off Connect DDIO clkn to
DQS_BUS from complementary DQSn

Use DQ input phase alignment

Turned off.

The feature is for half-rate components; the design
uses full-rate memory components.

Use DQ input delay chain

Turned on.

Table 2–6. Advance Options (DQS IN)

Parameter

Sub-options

Value

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