Maxim Integrated 71M6521BE Energy Meter IC Family Software - Manual (Page 66)

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 66 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Power Factor Measurement
The power-factor option (not compiled in the executable Demo Code) provides both instantaneous and accumulated
(over fractions of an hour) display of power factor by phase. All power factor calculations are performed using floating
point variables.
The power factor (PF = cos ϕ) calculation is based on the equations:
P = S * cos ϕ = S * PF
==> PF = P/S,
with P = real energy, S = apparent energy, PF = power factor
or VAh divided by Wh.
5.4.4 Watchdog Timer
The Demo Code revision 4.03 uses only the hardware watchdog timer provided by the 80515. This fixed-duration timer
is controlled with SFR register WDI (0xE8).
The software watchdog timer is described in section 6.3.4, but should not be used. The hardware watchdog
timer is more reliable since it cannot be accidentally disabled.
The hardware watchdog timer requires a refresh by the MPU firmware, i.e. bit 7 of WDI set, at least every 1.5 seconds.
If this refresh does not occur, the hardware watchdog timer overflows, and the 80515 is reset as if RESETZ were pulled
low. When overflow occurs, the bit WD_OVF is set in the configuration RAM. Using the WD_OVF bit, the MPU can
determine whether a reset or a hardware watchdog timer overflow occurred. The WD_OVF bit is cleared when
RESETZ is pulled low.
Note: The bits of the WDI register (SFR 0xE8) should not be individually set or reset. Instead, byte operations should
be used.
The following macro code should be used for resetting (clearing) the watchdog, IE_RTC or IE_XFER bits:
#define WD_RST_ 0xFF // WatchDog bit.
#define IE_RTC_ 0x02 // RTC ticked.
#define IE_XFER_ 0x01 // XFER data available.
#define RESET_WD() IFLAGS = WD_RST_;
#define CLR_IE_XFER() IFLAGS = ~ IE_XFER_ & 0x7F ; // 0x7E
#define CLR_IE_RTC() IFLAGS = ~ IE_RTC_ & 0x7F ; // 0x7D
5.4.5 Real-Time Clock (RTC)
The RTC is accessible through the I/O RAM (Configuration RAM) registers RTC_SEC through RTC_YR (addresses
0x2015 through 0x201B), as described in the data sheets.
Since the RTC runs on a much slower clock than the MPU, only one write operation can be performed per RTC clock
cycle. This means that write operations to set the RTC must be separated by at least 396us. The sample code uses a
software timer to perform this delay, so any code modification must make sure that hardware timer 1 is still useable for
the RTC functions.