Maxim Integrated 71M6521BE Energy Meter IC Family Software - Manual (Page 10)

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 10 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Table 6-30: Serial 1 Modes .......................................................................................................................................... 124
Table 6-31: The S1CON Register ................................................................................................................................ 124
Table 6-32: The S1CON Bit Functions ......................................................................................................................... 125
Table 6-33: The IEN0 Register ..................................................................................................................................... 127
Table 6-34: The IEN0 Bit Functions ............................................................................................................................. 127
Table 6-35: The IEN1 Register ..................................................................................................................................... 127
Table 6-36: The IEN1 Bit Functions ............................................................................................................................. 127
Table 6-37: The IP0 Register ....................................................................................................................................... 127
Table 6-38: The IP0 Bit Functions ................................................................................................................................ 128
Table 6-39: The WDTREL Register ............................................................................................................................. 128
Table 6-40: The WDTREL Bit Functions ...................................................................................................................... 128
Table 6-41: The IEN0 Register ..................................................................................................................................... 129
Table 6-42: The IEN0 Bit Functions ............................................................................................................................. 129
Table 6-43: The IEN1 Register ..................................................................................................................................... 129
Table 6-44: The IEN1 Bit Functions ............................................................................................................................. 129
Table 6-45: The IEN2 Register ..................................................................................................................................... 129
Table 6-46: The IEN2 Bit Functions ............................................................................................................................. 129
Table 6-47: The TCON Register .................................................................................................................................. 130
Table 6-48: The TCON Bit Functions ........................................................................................................................... 130
Table 6-49: The IRCON Register ................................................................................................................................. 130
Table 6-50: The IRCON Bit Functions .......................................................................................................................... 130
Table 6-51: The T2CON Register ................................................................................................................................ 131
Table 6-52: The T2CON Bit Functions ......................................................................................................................... 131
Table 6-53: Priority Level Groups ................................................................................................................................. 131
Table 6-54: External MPU Interrupts ............................................................................................................................ 132
Table 6-55: Control Bits for External Interrupts ............................................................................................................ 132
Table 6-56: The IP0 Register ....................................................................................................................................... 132
Table 6-57: The IP1 Register ....................................................................................................................................... 132
Table 6-58: Priority Levels ............................................................................................................................................ 132
Table 6-59: Polling Sequence ...................................................................................................................................... 133
Table 6-60: Interrupt Vectors........................................................................................................................................ 133