Maxim Integrated 71M6521BE Energy Meter IC Family Software - Manual (Page 126)

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 126 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
6.3.4 Software Watchdog Timer
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset,
the watchdog timer is disabled and all registers are set to zero.
Software Watchdog Timer structure
The watchdog consists of a 16-bit counter (wdt), a reload register (WDTREL), prescalers (by 2 and by 16), and control
logic.
Figure 6-3: Watchdog Block Diagram
6.3.4.1 WD Timer Start Procedure
During an active internal reset signal, the programmer can start the watchdog later. It will occur when the SWD signal
becomes active. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active.
When the WDT registers enters the state 0x7CFF , an asynchronous WDTS signal will become active. The signal
WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or changing
the state of the WDT timer.
/
2
/
16
wdtl wdth
wdtrel
Contr ol
logic
fclk/12
wdts
swd
wdt
swdt
0 7 8 14
7 6 0