IEI Integration SPCIE-5100DX - Manual (Page 40)

SPCIE-5100DX PICMG 1.3 CPU Card
Page 26
Figure 3-7: 34-pin FDD Connector Location
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 GND 2 REDUCE WRITE
3 GND 4 N/C
5 N/C 6 N/C
7 GND 8 INDEX#
9 GND 10 MOTOR ENABLE A#
11 GND 12 DRIVE SELECT B#
13 GND 14 DRIVE SELECT A#
15 GND 16 MOTOR ENABLE B#
17 GND 18 DIRECTION#
19 GND 20 STEP#
21 GND 22 WRITE DATA#
23 GND 24 WRITE GATE#
25 GND 26 TRACK 0#
27 GND 28 WRITE PROTECT#
29 GND 30 READ DATA#
31 GND 32 SIDE 1 SELECT#
33 GND 34 DISK CHANGE#
Table 3-8: 34-pin FDD Connector Pinouts