Atec Agilent-J2300E - Manual (Page 78)

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HSSI (56 kb/s – 52 Mb/s)
General
This interface comprises a plug-in module (J3762B) suitable for plugging into
the J2300C/D/E Agilent Advisor mainframe and J2900A High Speed undercradle.
The J3762B supports frame-based technologies such as Frame Relay (CIR and
SLA), HDLC, SDLC, and PPP in addition to BERT.
Common to Inputs and Outputs:
Connectors:
Two 50 pin SCSI (one to DCE, one to DTE)
Type:
Latch Blocks without rails
Clocking:
Recovered or
Internal (selectable from 56 kb/s - 52 Mb/s)
Control Signal:
DCE: CA, TM
DTE: TA
Loop Control:
DTE: None, Local DTE, Local Line, Remote Line
DCE: LC
Electrical:
EIA-612
EIA-613
Monitored:
Signal:
DTE: SD
DCE: RD
Clock:
From DCE: ST, RT
From DTE: TT
Status:
DCE Ready: TA
DTE Ready: CA
Loopback:
A: LA
B: LB
Test Mode: TM
BERT:
Analyze bit error ratio (BER) patterns in the physical layer
frame payload or in the ATM cell payload.
Generate bit error ratio (BER) patterns in the physical layer frame payload or
in the ATM cell payload
Transmission of 4000 byte BER user pattern in WAN
ATM and WAN Interface
Specifications
(continued)