Rainbow Electronics AT89C5122 - Manual (Page 81)

81
AT8xC5122/23
4202E–SCR–06/06
Reset Value = 1000 0000b
Table 46. Smart Card UART Interface Status Register -
SCISR (S:ADh, SCRS=0)
7 6 5 4 3 2 1 0
SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE
Bit Number Bit Mnemonic Description
7 SCTBE
UART Transmit Buffer Empty Status
This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card
UART.
It is cleared by hardware when SCIBUF register is written.
6 CARDIN
Card Presence Status
This bit is set by hardware if there is a card presence (debouncing filter has to be done by software).
This bit is cleared by hardware if there is no card presence.
5 ICARDOVF
Card Current Overflow Status
This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61
on page 94)
It is cleared by hardware.
4 VCARDOK
Card Voltage Correct Status
This bit is set when the output voltage is within the voltage range specified by VCARD[1:0] in SCICR register.
It is cleared otherwise.
3 SCWTO
Waiting Time Counter Timeout Status
This bit is set by hardware when the Waiting Time Counter has expired.
It is cleared by the reload of the counter or by the reset of the SCIB.
2 SCTC
UART Transmitted Character Status
This bit is set by hardware when the Smart Card UART has transmitted a character. If character repetition mode is
selected, this bit will be set only after a successful transmission. If the last allowed repetition in not successful, this
bit will not be set.
It is cleared by software when this register is read.
1 SCRC
UART Received Character Status
This bit is set by hardware when the Smart Card UART has received a character
It is cleared by hardware when SCIBUF register is read. If character repetition mode is selected, this bit will be set
only after a successful reception. If the last allowed repetition is still unsuccessful, this bit will be set to let the user
read the erroneous value if necessary.
0 SCPE
Character Reception Parity Error Status
This bit is set when a parity error is detected on the received character.
It is cleared by software when this register is read. If character repetition mode is selected, this bit will be set only
if the ICC report an error on the last allowed repetition of a TERMINAL transmission, or if a reception parity error
is found on the last allowed ICC character repetition.