Rainbow Electronics AT89C5122 - Manual (Page 143)

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AT8xC5122/23
4202E–SCR–06/06
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests.
Figure 89 gives a logical view of the above statements.
Figure 89. SPI Interrupt Requests Generation
Registers There are three registers in the module that provide control, status and data storage
functions. These registers are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON) The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configures the SPI module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI module
• Frees the SS pin for a general-purpose
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF