Rainbow Electronics ATF1516ASL User Manual
Features, Enhanced features

1
High-
performance
EE-based CPLD
ATF1516AS
ATF1516ASL
Preliminary
Features
•
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 256 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 160, 192, 208 pins
– 10 ns Maximum Pin-to-pin Delay
– Registered Operation Up To 100 MHz
– Enhanced Routing Resources
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Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
•
Advanced Power Management Features
– Automatic 3 mA Standby for “L” Version (Maximum)
– Pin-controlled 4 mA Standby Mode (Typical)
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
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Available in Commercial and Industrial Temperature Ranges
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Available in 160-lead PQFP, 192-pin PGA, and 208-lead RQFP Packages
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Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
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JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
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Fast In-System Programmability (ISP) via JTAG
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PCI-compliant
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3.3 or 5.0V I/O Pins
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Security Fuse Feature
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
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Output Enable Product Terms
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D-latch Mode
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Combinatorial Output with Registered Feedback within Any Macrocell
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Three Global Clock Pins
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ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
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Fast Registered Input from Product Term
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Programmable “Pin-keeper” Option
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V
CC
Power-up Reset Option
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Pull-up Option on JTAG Pins TMS and TDI
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Advanced Power Management Features
– Edge Controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0994D–09/99
Document Outline
- Features
- Enhanced Features
- Block Diagram
- Description
- Programmable Pin-keeper Option for Inputs and I/Os
- Input Diagram
- I/O Diagram
- Speed/Power Management
- Design Software Support
- Power-up Reset
- Security Fuse Usage
- Programming
- ISP Programming Protection
- Timing Model
- Input Test Waveforms and Measurement Levels
- Output AC Test Loads:
- Power-down Mode
- JTAG-BST Overview
- JTAG Boundary-scan Cell (BSC) Testing
- BSC Configuration Pins and Macrocells (Except JTAG TAP Pins)
- BSC Configuration for Macrocell
- PCI Compliance
- PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode
- PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode
- Ordering Information
- Using “C” Product for Industrial