Rainbow Electronics AT89C5122 - Manual (Page 43)

43
AT8xC5122/23
4202E–SCR–06/06
Figure 19. PLL Programming Flow
Clock Tree Architecture The clock controller outputs several different clocks as shown in Figure 20:
• a clock for the CPU core
• a clock for the peripherals which is used to generate the timers, watchdog, SPI,
UART, and ports sampling clocks. This divided clock will be used to generate the
alternate card clock.
• a clock for the USB
• a clock for the SCIB controller
• a clock for the DC/DC converter
These clocks are enabled or not depending on the power reduction mode as detailed in
Section “Power Management”, page 180.
These clocks are generated using four presacalers defined in the table below:
PLL
Programming
Configure Dividers
N3:0= xxxxb
R3:0= xxxxb
Enable PLL
PLLEN= 1
PLL Locked?
PLOCK= 1?
Prescaler Register Reload Factor Function
PR1 CKRL CKRL[0:3] CPU & Peripheral clocks
PR2 SCICLK SCICLK[0:5] Smart card
PR3 SCSR ALTKPS[0:1] Alternate card
PR4 DCCKPS DCCKPS[3:0] DC/DC