Rainbow Electronics AT89C5131 - Manual (Page 28)

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AT89C5131
4136A–USB–03/03
Figure 14. Flash Memory Architecture
FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 14):
1. The memory array (user space) 32 Kbytes
2. The Extra Row
3. The Hardware security bits
4. The column latch registers
User Space This space is composed of a 32 Kbytes Flash memory organized in 256 pages of 128
bytes. It contains the user’s application code.
Extra Row (XRow) This row is a part of FM0 and has a size of 128 bytes. The extra row may contain infor-
mation for bootloader usage.
Hardware Security Space The hardware security space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software. The 4 LSB can only be read by software
and written by hardware in parallel mode.
Column Latches The column latches, also part of FM0, have a size of full page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XRow and Hardware security byte).
Overview of FM0
Operations The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
• Map the memory spaces in the adressable space
• Launch the programming of the memory spaces
• Get the status of the Flash memory (busy/not busy)
• Select the Flash memory FM0/FM1.
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting this bit takes precedence on the EXTRAM bit in AUXR register.
7FFFh
32 Kbytes
Flash Memory
FM0
0000h
Hardware Security (1 Byte)
Column Latches (128 Bytes)
User Space
Extra Row (128 Bytes)
3 Kbytes
Flash Memory
FM1
Boot Space
FFFFh
F400h
FM1 mapped between FFFFh and
F400h when bit ENBOOT is set in
AUXR1 register