Rainbow Electronics AT89C5131 - Manual (Page 142)

142
AT89C5131
4136A–USB–03/03
Table 94. UEPINT Register
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
Reset Value = 00h
7 6 5 4 3 2 1 0
- EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
Bit Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is always 0. Do not set this bit.
6 EP6INT
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
5 EP5INT
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
4 EP4INT
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
3 EP3INT
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
2 EP2INT
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
1 EP1INT
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
0 EP0INT
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.