Rainbow Electronics AT89C5131 User Manual
Page 23
23
AT89C5131
4136A–USB–03/03
Table 27. CKCON1 (S:AFh)
Clock Control Register 1
Reset Value = 0000 0000b
Table 28. PLLCON (S:A3h)
PLL Control Register
Reset Value = 0000 0000b
Table 29. PLLDIV (S:A4h)
PLL Divider Register
Reset Value = 0000 0000
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit Number
Bit
Mnemonic Description
7-1
-
Reserved
The value read from this bit is always 0. Do not set this bit.
0
SPIX2
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
PLLEN
PLOCK
Bit Number
Bit
Mnemonic Description
7-3
-
Reserved
The value read from this bit is always 0. Do not set this bit.
2
-
Reserved
The value read from this bit is always 0. Do not set this bit.
1
PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0
PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
7
6
5
4
3
2
1
0
R3
R2
R1
R0
N3
N2
N1
N0
Bit Number
Bit
Mnemonic Description
7-4
R3:0
PLL R Divider Bits
3-0
N3:0
PLL N Divider Bits