Rainbow Electronics AT89C5131 - Manual (Page 20)

20
AT89C5131
4136A–USB–03/03
Figure 6. Crystal Connection
PLL
PLL Description The AT89C5131 PLL is used to generate internal high frequency clock (the USB Clock)
synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is
used to generate the USB interface clock. Figure 7 shows the internal structure of the
PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 7) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Fi g u re 8 ) . V a l u e o f t h e f i l t e r c o m p o n e n t s a r e d e t a i l e d i n th e S e c t i o n “ DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
REF
pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 7. PLL Block Diagram and Symbol
Figure 8. PLL Filter Connection
The typical values are: R = 100
Ω
, C1 = 10 nf, C2 = 2.2 nF.
VSS
X1
X2
Q
C1
C2
PLLEN
PLLCON.1
N3:0
N divider
R divider
VCO USB Clock
USBclk
OSCclk R 1 + ( ) ×
N 1 +
----------------------------------------------- =
OSC
CLOCK PFLD
PLOCK
PLLCON.0
PFILT
CHP
Vref
Up
Down
R3:0
USB
CLOCK
USB Clock Symbol
VSS
PFILT
R
C1
C2
VSS