Texas Instruments TMS380C26 - Manual (Page 90)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
90
PARAMETER MEASUREMENT INFORMATION
normal completion with delayed start†
SBCLK
T1 T(W or 2) T3 T4
SDTACK
SBERR
SHALT
TH T1
rerun cycle with delayed start †
SBCLK
T1 T2 T3 T4 THB THE
SDTACK
SBERR
SHALT
T1
SOWN
† Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms shown.
Figure 45. 68xxx Bus Halt and Retry Cycle Waveforms