Texas Instruments TMS380C26 - Manual (Page 85)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
85
PARAMETER MEASUREMENT INFORMATION
68xxx mode DMA write timing
NO. PARAMETER MIN MAX UNIT
208a
Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition
on this cycle
15 ns
208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle 15 ns
209 Pulse duration, SAS, SUDS, and SLDS high
tc(SCK)+
tw(SCKL) – 25
ns
211 Delay from SBCLK high in T2 cycle to SUDS and SLDS active 25 ns
211a Delay of output data valid to SUDS and SLDS no longer high tw(SCKL) – 15 ns
212 Delay from SBCLK low to address valid 25 ns
215 Pulse duration, SALE and SXAL high tc(SCK) – 25 ns
216 Delay from SBCLK high to SALE or SXAL high 25 ns
216a Hold of SALE or SXAL low after SUDS and SAS high tw(SCKL) – 15 ns
217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns
218 Hold of address valid after SALE, SXAL low tw(SCKH) – 15 ns
219 Delay from SBCLK low in T2 cycle to output data and parity valid 39 ns
221 Hold of output data, parity valid after SUDS and SLDS high tc(SCK) – 15 ns
222 Delay from SBCLK high to SAS low 25 ns
223W Delay from SBCLK low to SUDS, SLDS, and SAS high 25 ns
225W Delay from SBCLK high in T4 cycle to SDBEN high 25 ns
225WH Hold of SDBEN low after SUDS and SLDS high tw(SCKL) – 25 ns
233 Setup of address valid before SALE or SXAL no longer high tw(SCKL) – 15 ns
233a Setup of address valid before SAS no longer high tw(SCKL) – 15 ns
237W Delay from SBCLK high in T1 cycle to SDBEN low 25 ns
239 SAS pulse duration
2tc(SCK)+
tw(SCKH) – 30
ns
243 Pulse duration, SUDS and SLDS
tc(SCK)+
tw(SCKH) – 25
ns