Texas Instruments TMS380C26 - Manual (Page 88)

TMS380C26 NETWORK COMMPROCESSOR
SPWS010A–APRIL
1992–REVISED MARCH 1993
88
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TEXAS
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PARAMETER MEASUREMENT INFORMATION
User Bus Exchange SIF Master
T1 I2 I1 T4 T3 T2
SOWN
SDDIR
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
SRNW
SAS, SUDS,
SLDS
SBRQ
(see Note A)
SIF Outputs:
SDTACK
SBGR
SBCLK
SIF Inputs:
230
220
224b
240
220
224d
HI-Z
HI-Z
READ
WRITE
SIF
WRITE
READ
240
223b
NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system
interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
Figure 43. 68xxx Mode Bus Arbitration Timing, SIF Returns Control