Texas Instruments TMS380C26 - Manual (Page 82)

TMS380C26 NETWORK COMMPROCESSOR
SPWS010A–APRIL
1992–REVISED MARCH 1993
82
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PARAMETER MEASUREMENT INFORMATION
SOWN
(see Note B)
SDDIR
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
SRNW
SAS, SLDS,
SUDS
SBRQ
(see Note A)
SIF Outputs:
SBERR,
SDTACK,
SBBSY
SBGR
SBCLK
SIF Inputs:
SIF Master Bus Exchange User Master
T2 T1 TX I2 I1 (T4)
Output
WRITE
READ
SIF
230
224a
224c
212
208a 208b 241
241
208b
208a
230
READ
WRITE
HI-Z
(Input)
241a
NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the
system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
B. While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.
Figure 40. 68xxx Mode Bus Arbitration Timing, SIF Takes Control