Texas Instruments TMS380C26 - Manual (Page 58)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
58
PARAMETER MEASUREMENT INFORMATION
ethernet timing of RCV signals — end of frame
NO. PARAMETER MIN TYP MAX UNIT
320 CRSSET
Setup time of CRS low before RXC no longer low to determine if last data bit ”seen” on
previous RXC no longer low (see Note 18)
20 ns
321 CRSHLD
Hold time of CRS low after RXC no longer low, to determine if last data bit ”seen” on
previous RXC no longer low
0 ns
322 XTRCYC Number of extra RXC clock cycles after last data bit (CRS pin is low) (see Note 18) 0 5 cycle
NOTE 18: TMS380C26 will operate correctly even with no extra RXC clock cycles, providing that CRS does not remain asserted longer than
2
µ
s (see timing spec, NDRXC). Providing no extra clocks affect receive startup timing, see timing spec, SAMDLY.
CRS
RXC
RXD
322
320
321
Last
Data Bit
Figure 24. Ethernet Timing of RCV Signals — End Of Frame