Texas Instruments TMS380C26 - Manual (Page 69)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
69
PARAMETER MEASUREMENT INFORMATION
80x8x mode DMA read timing
NO. PARAMETER MIN MAX UNIT
205
Setup of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid before SBCLK in T3 cycle no
longer high
15 ns
206
Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if
parameters 207a and 207b not met
15 ns
207a Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SRD high 0 ns
207b Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SDBEN no longer low 0 ns
208a
Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition on
this cycle
15 ns
208b Hold of asynchronous signal SRDY after SBCLK low to guarantee recognition on this cycle 15 ns
212 Delay from SBCLK low to address valid 25 ns
214†
Delay from SBCLK low in T1 cycle to SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-im-
pedance
25 ns
215 Pulse duration, SALE and SXAL high tc(SCK) – 25 ns
216 Delay from SBCLK high to SALE or SXAL high 25 ns
216a Hold of SALE or SXAL low after SRD high tw(SCKL) – 15 ns
217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns
218 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SALE or SXAL low tw(SCKH) – 15 ns
223R Delay from SBCLK low in T4 cycle to SRD high (see Note 23) 25 ns
225R Delay from SBCLK low in T4 cycle to SDBEN high 25 ns
226† Delay from SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-impedance to SRD low 0 ns
227R Delay from SBCLK low in T2 cycle to SRD low 25 ns
229†
Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-impedance after SBCLK low in
T1 cycle
0 ns
231 Pulse duration, SRD low 2tc(SCK) – 30 ns
233
Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL no longer
high
tw(SCKL) – 15 ns
237R Delay from SBCLK high in the T2 cyle to SDBEN low 25 ns
247 Setup of data valid before SRDY low if parameter 208a not met 0 ns
† This specification has been characterized to meet stated value.
NOTE 23: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.