Texas Instruments TMS380C26 - Manual (Page 66)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
66
PARAMETER MEASUREMENT INFORMATION
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
(see Note A)
SRDY†
SDBEN
SDDIR
SRD
SWR
SIACK
SCS, SRSX,
SRS0–SRS2,
SBHE
Only SCS needs to be inactive.
All others are Don’t Care.
(High)
HI-Z HI-Z
HI-Z
Output Data Valid
261
261a
260 259
275
279
283R
282a
HI-Z
276
255
273a
273a
273a 272a
272a
272a
282R
† SRDY is an active-low bus ready signal. It must be asserted before data output.
NOTE A: In 8-bit 80x8x mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.
Figure 31. 80x8x Interrupt Acknowledge Timing – Second SIACK Pulse