Texas Instruments TMS380C26 - Manual (Page 83)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
83
PARAMETER MEASUREMENT INFORMATION
68xxx mode DMA read timing
NO. PARAMETER MIN MAX UNIT
205 Setup of input data valid before SBCLK in T3 cycle no longer high 15 ns
206 Hold of input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 15 ns
207a Hold of input data valid after data strobe no longer low 0 ns
207b Hold of input data valid after SDBEN no longer low 0 ns
208a
Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition
on this cycle
15 ns
208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle 15 ns
209 Pulse duration, SAS, SUDS, and SLDS high
tc(SCK)+
tw(SCKL) – 25
ns
210 Delay from SBCLK high in T2 cycle to SUDS and SLDS active 25 ns
212 Delay from SBCLK low to address valid 25 ns
214† Delay from SBCLK low in T2 cycle to SAD high-impedance 25 ns
215 Pulse duration, SALE and SXAL high tc(SCK) – 25 ns
216 Delay from SBCLK high to SALE or SXAL high 25 ns
216a Hold of SALE or SXAL low after SUDS and SAS high tw(SCKL) – 15 ns
217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns
218 Hold of address valid after SALE, SXAL low tw(SCKH) – 15 ns
222 Delay from SBCLK high to SAS low 25 ns
223R Delay from SBCLK low in T4 cycle to SUDS, SLDS, and SAS high (see Note 25) 25 ns
225R Delay from SBCLK low in T4 cycle to SDBEN high 25 ns
229† Hold of SAD high-impedance after SBCLK low in T4 cycle 0 ns
233 Setup of address valid before SALE or SXAL no longer high tw(SCKL) – 15 ns
233a Setup of address valid before SAS no longer high tw(SCKL) – 15 ns
237R Delay from SBCLK high in the T2 cycle to SDBEN low 25 ns
239 Pulse duration, SAS, SUDS, and SLDS
2tc(SCK)+
tw(SCKH) – 30
ns
247 Setup of data valid before SDTACK low if parameter 208a not met 0 ns
† This specification has been characterized to meet stated value.
NOTE 25: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.