Texas Instruments TMS380C26 - Manual (Page 84)

TMS380C26 NETWORK COMMPROCESSOR
SPWS010A–APRIL
1992–REVISED MARCH 1993
84
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PARAMETER MEASUREMENT INFORMATION
SALE
SDBEN
(see Note A)
SDDIR
SDTACK
(see Notes B and C)
SADL0–SADH7,
SADH0–SADL7,
SPH, SPL
SXAL
SRNW
SUDS,
SLDS
SAS
(see Note A)
SBCLK
HI-Z Data In Address
S7 S6 S5 S4 S3 S2 S1
T1 T4 T3 T2 T1 TX T4
207a
207b
225R
212
233 233
217
222
215
(High)
223R
216
TWAIT
V
233a
217
206
208a
208b
214
239
216
215
218
210
209
209
216a
229
218
239
237R
247† Extended Address
212
205
† If parameter 208a is not met, then valid data must be present before SDTACK goes low.
NOTES: A. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
B. All VSS pins should be routed to minimize inductance to system ground.
C. On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN
becomes no longer active.
Figure 41. 68xxx Mode DMA Read Timing