Texas Instruments TMS380C26 - Manual (Page 51)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
51
PARAMETER MEASUREMENT INFORMATION
memory bus timing: external bus master write to TMS380C26
NO. PARAMETER MIN MAX UNIT
96 Setup time of valid data/parity before MBCLK2 falling edge, external bus master write 21 ns
97 Hold time of valid data/parity after MBCLK2 low, external bus master write 0 ns
98 Setup time of MDDIR high before MBCLK2 falling edge, external bus master write 21 ns
99 Hold time of MDDIR high after MBCLK2 low, external bus master write 0 ns
MBCLK1
MAX0, MAX2
96
MAXPH,
MAXPL,
MADH0–MADH7,
MADL0–MADL7
Data/Pty
Address In
MDDIR
MACS
Address In
97
99
98
95
94
Address In Address In
Figure 16. Memory Bus Timing: External Bus Master Write To TMS380C26