Texas Instruments TMS380C26 - Manual (Page 63)

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
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HOUSTON, TEXAS
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63
PARAMETER MEASUREMENT INFORMATION
80x8x DIO write timing
NO. PARAMETER MIN MAX UNIT
255 Delay from SRDY low to either SCS or SWR high 15 ns
256 Pulse duration, SRAS high 30 ns
262 Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SCS or SWR no longer low 25 ns
263 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SCS or SWR high 25 ns
264 Setup of SRSX, SRS0–SRS2, SCS, and SBHE to SRAS no longer high (see Note 21) 30 ns
265 Hold of SRSX, SRS0–SRS2, SCS, and SBHE after SRAS low 15 ns
266a Setup of SRAS high to SWR no longer high (see Note 22) 25 ns
267† Setup of SRSX, SRS0–SRS2 before SWR no longer high (see Note 21) 15 ns
268 Hold of SRSX, SRS0–SRS2 valid after SWR no longer low (see Note 22) 0 ns
272a Setup time of SRD, SWR, and SIACK high from previous cycle to SWR no longer high 55 ns
273a Hold time of SRD, SWR, and SIACK high after SWR high 55 ns
276‡
Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following
access to the SIF (see
TMS380 Second-Generation Token Ring User’s Guide, SPWU005, subsection
3.4.1.1.1)
275 Delay from SWR or SCS high to SRDY high (see Note 21) 35 ns
279§ Delay from SWR high to SRDY high impedance 65 ns
280 Delay from SWR low to SDDIR low (see Note 21) 25 ns
281 Delay from SWR high to SDDIR high (see note 21) 55 ns
281a Hold of SDDIR low after SWR no longer active (see Note 21) 0 ns
282b
Delay from SDBEN low to SRDY low (see TMS380 Second Generation Token-Ring
If SIF register is
ready (no waiting
required)
0 35
ns 282b
y ( g
User’s Guide, SPWU005, subsection 3.4.1.1.1) If SIF register is
not ready (waiting
required)
0 4000
ns
282W Delay from SDDIR low to SDBEN low 25 ns
283W Delay from SCS or SWR high to SDBEN no longer low 25 ns
286 Pulse duration SWR high between DIO accesses (see Note 21) 55 ns
† It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
‡ This specification has been characterized to meet stated value.
§ This specification is provided as an aid to board design.
NOTES: 21. The “inactive” chip select is SIACK in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge
cycles.
22. In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters
266a and 264 are irrelevant, and parameter 268 must be met.