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Renesas RJJ10J1643-0101 User Manual

Page 129

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Rev.1.01 2007.02.16
RJJ10J1643-0101

127

(Interrupt)

If overflow interrupt requests are enabled, specify RAPI_OVERFLOW. If

compare match A, compare match B, compare match C, or compare

match D interrupt requests are enabled, specify

RAPI_COMPARE_MATCH_A, RAPI_COMPARE_MATCH_B,

RAPI_COMPARE_MATCH_C, or RAPI_COMPARE_MATCH_D,

respectively. When not specifying interrupts, select “No interrupt

requests.”

(Counter clear)

To specify GRA compare match for the cause of counter clear, specify

RAPI_COUNT_CLEAR_A.

• Specifiable definition values when timer RD is used (RAPI_TIMER_RD0 to

RAPI_TIMER_RD4 specified)

(Count

source)

Specify one from [RAPI_TRD_F1, RAPI_TRD_F2, RAPI_TRD_F4,

RAPI_TRD_F8, RAPI_TRD_F32, RAPI_TRD_F40M]. The default is

RAPI_TRD_F1.

(Operating

states set)

Specify one from { RAPI_TIMER_ON, RAPI_TIMER_OFF }. The default

value is RAPI_TIMER_OFF.

(Interrupt)

If overflow interrupt requests are enabled, specify RAPI_OVERFLOW.

Similarly, if compare match A, compare match B, compare match C, or

compare match D interrupt requests are enabled, specify

RAPI_COMPARE_MATCH_A, RAPI_COMPARE_MATCH_B,

RAPI_COMPARE_MATCH_C, or RAPI_COMPARE_MATCH_D,

respectively. If no interrupts are specified, “No interrupt request” is set.

(Counter clear)

To specify GRA, GRB, GRC, or GRD compare match for the cause of

counter clear, specify RAPI_COUNT_CLEAR_A,

RAPI_COUNT_CLEAR_B, RAPI_COUNT_CLEAR_C, or

RAPI_COUNT_CLEAR_D, respectively.

(Synchronization) If the timer is synchronized on channels 0 and 1, specify

RAPI_TIMER_SYNC. If synchronization is not specified, “Channels 0 and

1 operate independently” is set.

[data2]

(M16C)

Specify a pointer to the array in which the interrupt priority level is stored.

[0]: Specify the IC/OC base timer interrupt priority level (0–7).

[1]: Specify the IC/OC interrupt 0 priority level (0–7).

[2]: Specify the IC/OC interrupt 1 priority level (0–7).

(R8C)

Specify a pointer to the array in which the interrupt priority level is stored.

[0]: Specify the timer C interrupt priority level (0–7).

[1]: Specify the compare match 0 interrupt priority level (0–7).

[2]: Specify the compare match 1 interrupt priority level (0–7).

(H8/300H)

Specify

0.

[data3]