Renesas RJJ10J1643-0101 - Manual (Page 112)

Rev.1.01 2007.02.16
RJJ10J1643-0101 110
(Operating
states set)
Specify one from [RAPI_TIMER_ON, RAPI_TIMER_OFF]. The default is
RAPI_TIMER_OFF.
(Interrupt) If overflow interrupt requests are enabled, specify RAPI_OVERFLOW. If
input capture A, input capture B, input capture C, or input capture D
interrupt requests are enabled, specify RAPI_INPUT_CAPURE_A,
RAPI_INPUT_CAPURE_B, RAPI_INPUT_CAPURE_C, or
RAPI_INPUT_CAPURE_D, respectively. When not specifying interrupts,
select “No interrupt requests.”
(Counter clear) To specify GRA, GRB, GRC, or GRD input capture for the cause for
which the counter is cleared, select RAPI_COUNT_CLEAR_A,
RAPI_COUNT_CLEAR_B, RAPI_COUNT_CLEAR_C, or
RAPI_COUNT_CLEAR_D, respectively. If cleared at the same time a
synchronously operating counter on another channel is cleared, select
RAPI_COUNT_CLEAR_SYNC.
(Synchronization
)
If timers on channels 0 and 1 are to be synchronized, select
RAPI_TIMER_SYNC. When not specifying synchronization, select
“Channels 0 and 1 operate independently.”
(Clock for digital
filter)
Specify one from [RAPI_TRD_FILTER_F1, RAPI_TRD_FILTER_F8,
RAPI_TRD_FILTER_F32, RAPI_TRD_FILTER_F]. The default is
RAPI_TRD_FILTER_F32.
[data2]
(M16C)
Specify a pointer to the array in which the interrupt priority level is stored.
[0]: Specify the IC/OC base timer interrupt priority level (0–7).
[1]: Specify the IC/OC interrupt 0 priority level (0–7).
[2]: Specify the IC/OC interrupt 1 priority level (0–7).
(R8C)
When timer RD is used (RAPI_TIMER_RD0 or RAPI_TIMERRD1 specified),
specify a pointer to the variable that contains the interrupt priority level (0–7) to be
set in the interrupt control register. When timer RD is not used, specify a pointer to
the following array that contains the interrupt priority level
[0]: Specify the timer C interrupt priority level (0–7).
[1]: Specify the compare match 0 interrupt priority level (0–7).
[2]: Specify the compare match 1 interrupt priority level (0–7).
(H8/300H)
Specify the interrupt priority level (0–1) to be set in the interrupt control register. For
the CPUs that do not have an interrupt control register, specify 0.
[data3]
(M16C)
Specify a pointer to the array in which the set value for the time measurement
control register is stored.
[0]: Specify the set value for time measurement control register 0.
[1]: Specify the set value for time measurement control register 1.