beautypg.com

Altera Stratix V Advanced Systems Development Board User Manual

Page 8

background image

1–4

Chapter 1: Overview

Development Board Component Blocks

Stratix V Advanced Systems Development Board

January 2014

Altera Corporation

Reference Manual

Memory interfaces

DDR3 SDRAM

Two 1024-MB interfaces with 64-bit data bus

Two 512-MB interfaces with 32-bit data bus

Four 4.5-MB QDRII+ SRAM with 18-bit data bus

One 72-MB MoSys Bandwidth Engine IC SRAM with 16-bit data bus
(16x10.3125 G XCVR)

One 32-MB serial flash

General user I/O

LEDs

16 user LEDs

Two HSMC interface LEDs transmit/receive (TX/RX)

One PCI Express LEDs

Push buttons and DIP switches

One CPU reset push button

Three general user push buttons

Eight general user DIP switches