Altera Stratix V Advanced Systems Development Board - Manual (Page 61)

Chapter 2: Board Components 2–51
Memory
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
K3 CASN 1.5-V SSTL Class I AK33 K17 Column address strobe
K9 CKE 1.5-V SSTL Class I AE31 K18 Clock enable
K7 CLK_N
Differential 1.5-V
SSTL Class I
AE32 P18 Differential output clock
J7 CLK_P
Differential 1.5-V
SSTL Class I
AD32 P19 Differential output clock
L2 CSN 1.5-V SSTL Class I AG33 L17 Chip select
E7 DM0 1.5-V SSTL Class I BA30 E21 Data write mask
D3 DM1 1.5-V SSTL Class I AG25 K22 Data write mask
E7 DM2 1.5-V SSTL Class I AN30 R21 Data write mask
D3 DM3 1.5-V SSTL Class I AJ28 T18 Data write mask
E7 DM4 1.5-V SSTL Class I AP27 H13 Data write mask
D3 DM5 1.5-V SSTL Class I AR29 M15 Data write mask
E7 DM6 1.5-V SSTL Class I AT27 U15 Data write mask
D3 DM7 1.5-V SSTL Class I BA28 A14 Data write mask
E3 DQ0 1.5-V SSTL Class I AY31 E20 Data bus
F7 DQ1 1.5-V SSTL Class I BC32 B20 Data bus
F2 DQ2 1.5-V SSTL Class I BB32 F22 Data bus
F8 DQ3 1.5-V SSTL Class I AW30 F21 Data bus
H3 DQ4 1.5-V SSTL Class I BD32 A22 Data bus
H8 DQ5 1.5-V SSTL Class I BD31 A20 Data bus
G2 DQ6 1.5-V SSTL Class I BB30 B22 Data bus
H7 DQ7 1.5-V SSTL Class I BC31 C21 Data bus
D7 DQ8 1.5-V SSTL Class I AF29 G22 Data bus
C3 DQ9 1.5-V SSTL Class I AF28 J21 Data bus
C8 DQ10 1.5-V SSTL Class I AG29 F20 Data bus
C2 DQ11 1.5-V SSTL Class I AG26 K21 Data bus
A7 DQ12 1.5-V SSTL Class I AG30 J22 Data bus
A2 DQ13 1.5-V SSTL Class I AG27 L21 Data bus
B8 DQ14 1.5-V SSTL Class I AK29 G20 Data bus
A3 DQ15 1.5-V SSTL Class I AG28 K20 Data bus
E3 DQ16 1.5-V SSTL Class I AT30 R22 Data bus
F7 DQ17 1.5-V SSTL Class I AR30 P21 Data bus
F2 DQ18 1.5-V SSTL Class I AP30 T22 Data bus
F8 DQ19 1.5-V SSTL Class I AU32 M22 Data bus
H3 DQ20 1.5-V SSTL Class I AJ31 U20 Data bus
H8 DQ21 1.5-V SSTL Class I AH30 V19 Data bus
G2 DQ22 1.5-V SSTL Class I AJ30 T21 Data bus
H7 DQ23 1.5-V SSTL Class I AH31 U21 Data bus
Table 2–24. FPGA2 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board
Reference
Schematic
Signal Name
I/O Standard Stratix V GX FPGA2 Device Pin Number Description