Altera Stratix V Advanced Systems Development Board - Manual (Page 53)

Chapter 2: Board Components 2–43
Memory
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
R3 A9 1.5-V SSTL Class I BD22 B26 Address bus
L7 A10 1.5-V SSTL Class I AU20 A28 Address bus
R7 A11 1.5-V SSTL Class I BC22 D27 Address bus
N7 A12 1.5-V SSTL Class I AW20 F28 Address bus
T3 A13 1.5-V SSTL Class I AT21 E27 Address bus
M2 BA0 1.5-V SSTL Class I BA21 F29 Bank address bus
N8 BA1 1.5-V SSTL Class I BD20 P26 Bank address bus
M3 BA2 1.5-V SSTL Class I AU21 B28 Bank address bus
K3 CASN 1.5-V SSTL Class I AK20 A29 Column address strobe
K9 CKE 1.5-V SSTL Class I AT20 H29 Clock enable
K7 CLK_N
Differential 1.5-V
SSTL Class I
AW22 H26 Differential output clock
J7 CLK_P
Differential 1.5-V
SSTL Class I
AV22 J27 Differential output clock
L2 CSN 1.5-V SSTL Class I BB21 E29 Chip select
E7 DM0 1.5-V SSTL Class I BB23 D24 Data write mask
D3 DM1 1.5-V SSTL Class I AN22 P29 Data write mask
E7 DM2 1.5-V SSTL Class I AU25 D26 Data write mask
D3 DM3 1.5-V SSTL Class I AL21 U23 Data write mask
E3 DQ0 1.5-V SSTL Class I AT24 E23 Data bus
F7 DQ1 1.5-V SSTL Class I AW23 D23 Data bus
F2 DQ2 1.5-V SSTL Class I AV23 B25 Data bus
F8 DQ3 1.5-V SSTL Class I AU23 E24 Data bus
H3 DQ4 1.5-V SSTL Class I BC23 B23 Data bus
H8 DQ5 1.5-V SSTL Class I BB24 F23 Data bus
G2 DQ6 1.5-V SSTL Class I AY24 A23 Data bus
H7 DQ7 1.5-V SSTL Class I BD23 A25 Data bus
D7 DQ8 1.5-V SSTL Class I AJ21 P27 Data bus
C3 DQ9 1.5-V SSTL Class I AM20 M28 Data bus
C8 DQ10 1.5-V SSTL Class I AJ19 M27 Data bus
C2 DQ11 1.5-V SSTL Class I AM22 N28 Data bus
A7 DQ12 1.5-V SSTL Class I AG19 L26 Data bus
A2 DQ13 1.5-V SSTL Class I AL20 P28 Data bus
B8 DQ14 1.5-V SSTL Class I AG20 N26 Data bus
A3 DQ15 1.5-V SSTL Class I AJ20 R27 Data bus
E3 DQ16 1.5-V SSTL Class I AR25 E26 Data bus
F7 DQ17 1.5-V SSTL Class I AV25 F24 Data bus
F2 DQ18 1.5-V SSTL Class I AW24 F25 Data bus
F8 DQ19 1.5-V SSTL Class I AU24 H24 Data bus
Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7)
Board
Reference
Schematic
Signal Name
I/O Standard Stratix V GX FPGA1 Device Pin Number Description