Altera Stratix V Advanced Systems Development Board - Manual (Page 17)

Chapter 2: Board Components 2–7
MAX V CPLD System Controller
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
MAX V CPLD System Controller
The board utilizes the 5M2210ZF256C4 System Controller, an Altera MAX V CPLD,
for the following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temperature monitoring
■ Fan control
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–2 illustrates the MAX V CPLD System Controller's functionality and external
circuit connections as a block diagram.
Transceiver Pairs
Chip-to-chip 8
HSMC 8
MoSys 16
PCI Express/PLX 8
Total Transceivers Used: 40
Table 2–3. Stratix V GX FPGA Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
Figure 2–2. MAX V CPLD System Controller Block Diagram
Information
Register
On-Board
USB-Blaster II
Si5538
Controller
Si570
Controller
SLD-HUB
PFL
MAX V System Controller
Power
Measurement
Results
Virtual-JTAG
PC
Temperature
Measurement
Results
FPGA1
LTC2418
Controller
MAX1619
Controller
FPGA2
Decoder Encoder
GPIO
JTAG Control
Flash
Control
Register
Si570
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator