Altera Stratix V Advanced Systems Development Board - Manual (Page 5)

January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
1. Overview
This document describes the hardware features of the Stratix ® V Advanced Systems
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The development board comes with two Stratix V GX FPGA devices to provide a
hardware platform for developing and prototyping high-performance and high-
bandwidth application designs. The board includes a wide range of peripherals and
memory interfaces to facilitate the development of Stratix V GX FPGA designs.
One FPGA Mezzanine Card (FMC) and one High-Speed Mezzanine Card (HSMC)
connector is available to add additional functionality via a variety of FMC and HSMC
cards available from both Altera and various partners.
Design advancements and innovations, such as the PCI Express hard IP
implementation, partial reconfiguration, and programmable power technology
ensure that designs implemented in the Stratix V GX FPGAs operate faster, with
lower power than in previous FPGA families.
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For more information on the following topics, refer to the respective documents or
page:
■ Stratix V device family, refer to the Stratix V Device Handbook .
■ PCI Express hard IP implementation, refer to the Stratix V Hard IP for PCI Express
User Guide .
■ List of the latest daughter cards available, refer to the Development Board
Daughtercards page of the Altera website.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification .