Altera Stratix V Advanced Systems Development Board - Manual (Page 48)

2–38 Chapter 2: Board Components
Components and Interfaces
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Figure 2–7 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. You can also use these pins as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Table 2–22 lists the HSMC port interface pin assignments, signal names, and
functions.
Figure 2–7. HSMC Signal and Bank Diagram
Bank 3
Power
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Power
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0
Table 2–22. HSMC Port Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
(J1)
Schematic Signal Name I/O Standard
Stratix V GX
FPGA2 Device Pin
Number
Description
40 HSMC_CLK_IN0 2.5-V BC8 Dedicated CMOS clock in
98 HSMC_CLK_IN_N1 LVDS or 2.5-V H18 LVDS or CMOS clock in 1
158 HSMC_CLK_IN_N2 LVDS or 2.5-V L9 LVDS or CMOS clock in 2
96 HSMC_CLK_IN_P1 LVDS or 2.5-V J18
LVDS or CMOS clock in 1 (secondary
clock)
156 HSMC_CLK_IN_P2 LVDS or 2.5-V M9
LVDS or CMOS clock in 2 (primary
clock)
39 HSMC_CLK_OUT0 LVDS or 2.5-V AR11 Dedicated CMOS clock out
97 HSMC_CLK_OUT_N1 LVDS or 2.5-V BD7 LVDS or CMOS clock out 1
157 HSMC_CLK_OUT_N2 LVDS or 2.5-V A10 LVDS or CMOS clock out 2
95 HSMC_CLK_OUT_P1 LVDS or 2.5-V BC7 LVDS or CMOS clock out 1
155 HSMC_CLK_OUT_P2 LVDS or 2.5-V B10 LVDS or CMOS clock out 2
30 HSMC_RX_P0 1.4-V PCML AB43 Transceiver receive channel