Altera Stratix V Advanced Systems Development Board - Manual (Page 70)

2–60 Chapter 2: Board Components
Memory
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Y8 MOSYS1_QBTX_N3 1.4-V PCML AD1 Transceiver input
AB7 MOSYS1_QBTX_N4 1.4-V PCML AB1 Transceiver input
Y6 MOSYS1_QBTX_N5 1.4-V PCML Y1 Transceiver input
AB5 MOSYS1_QBTX_N6 1.4-V PCML V1 Transceiver input
Y4 MOSYS1_QBTX_N7 1.4-V PCML T1 Transceiver input
AA11 MOSYS1_QBTX_P0 1.4-V PCML AK2 Transceiver input
W10 MOSYS1_QBTX_P1 1.4-V PCML AH2 Transceiver input
AA9 MOSYS1_QBTX_P2 1.4-V PCML AF2 Transceiver input
W8 MOSYS1_QBTX_P3 1.4-V PCML AD2 Transceiver input
AA7 MOSYS1_QBTX_P4 1.4-V PCML AB2 Transceiver input
W6 MOSYS1_QBTX_P5 1.4-V PCML Y2 Transceiver input
AA5 MOSYS1_QBTX_P6 1.4-V PCML V2 Transceiver input
W4 MOSYS1_QBTX_P7 1.4-V PCML T2 Transceiver input
F21 MOSYS1_RBIAS_0N 1.5-V CMOS — Calibration resistor
E21 MOSYS1_RBIAS_0P 1.5-V CMOS — Calibration resistor
F1 MOSYS1_RBIAS_1N 1.5-V CMOS — Calibration resistor
E1 MOSYS1_RBIAS_1P 1.5-V CMOS — Calibration resistor
M20 MOSYS1_READYN 1.5-V CMOS K15 Device ready
Y22 MOSYS1_REFCLK_N LVDS — Input reference clock
W22 MOSYS1_REFCLK_P LVDS — Input reference clock
M22 MOSYS1_RESETN_IN 1.5-V CMOS R15 Active low reset
P1 MOSYS1_SPI_SCLK 1.5-V CMOS D17 SPI slave clock
T1 MOSYS1_SPI_SDI 1.5-V CMOS C19 SPI data in or command
R2 MOSYS1_SPI_SDO 1.5-V CMOS F19 SPI data out
U2 MOSYS1_SPI_SS 1.5-V CMOS G19 SPI slave select, active low
H9 MOSYS1_VDD_KELVIN 1.0-V — VDD monitor point
H8 MOSYS1_VSS_KELVIN GND — VSS monitor point
FPGA2 MoSys (U14)
G20 MOSYS2_AMON_0 1.5-V CMOS — Analog monitor
B1 MOSYS2_AMON_1 1.5-V CMOS — Analog monitor
P22 MOSYS2_CLKDIVIDE 1.5-V CMOS B16 REFCLK divider enable
A21 MOSYS2_CMDARX_N0 1.4-V PCML AG3 Transceiver output
C20 MOSYS2_CMDARX_N1 1.4-V PCML AE3 Transceiver output
A19 MOSYS2_CMDARX_N2 1.4-V PCML AC3 Transceiver output
C18 MOSYS2_CMDARX_N3 1.4-V PCML AA3 Transceiver output
A17 MOSYS2_CMDARX_N4 1.4-V PCML W3 Transceiver output
C16 MOSYS2_CMDARX_N5 1.4-V PCML U3 Transceiver output
A15 MOSYS2_CMDARX_N6 1.4-V PCML R3 Transceiver output
C14 MOSYS2_CMDARX_N7 1.4-V PCML N3 Transceiver output
Table 2–27. MoSys MSR576 Interface Pin Assignments, Signal Names and Functions (Part 3 of 5)
Board Reference Schematic Signal Name I/O Standard
Stratix V GX FPGA
Device Pin Number
Description