Altera Stratix V Advanced Systems Development Board - Manual (Page 67)

Chapter 2: Board Components 2–57
Memory
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
J11 D4 1.5-V HSTL Class I AR19 AF10 E30 R34 Write data bus
G11 D5 1.5-V HSTL Class I AP19 AE9 D30 R33 Write data bus
E10 D6 1.5-V HSTL Class I AM19 AE12 A31 L32 Write data bus
D11 D7 1.5-V HSTL Class I AN20 AE10 B29 P34 Write data bus
C11 D8 1.5-V HSTL Class I AN19 AE11 C30 M34 Write data bus
B3 D9 1.5-V HSTL Class I AG18 AF14 V30 K32 Write data bus
C3 D10 1.5-V HSTL Class I AH18 AG13 W29 J33 Write data bus
D2 D11 1.5-V HSTL Class I AG17 AY10 Y30 J31 Write data bus
F3 D12 1.5-V HSTL Class I AJ18 BA10 V29 E35 Write data bus
G2 D13 1.5-V HSTL Class I AK18 AY12 Y29 K31 Write data bus
J3 D14 1.5-V HSTL Class I AL17 BC10 U29 F35 Write data bus
L3 D15 1.5-V HSTL Class I AL18 BB11 Y28 J34 Write data bus
M3 D16 1.5-V HSTL Class I AL19 BA12 V28 G35 Write data bus
N2 D17 1.5-V HSTL Class I AM17 BB12 G31 H35 Write data bus
H1 DOFFN 1.5-V HSTL Class I AP18 AP12 K29 A37 PLL disable
A6 K_N
Differential 1.5-V
HSTL Class I
AJ16 BD11 R28 H33 Write clock
B6 K_P
Differential 1.5-V
HSTL Class I
AJ15 BC11 T28 H34 Write clock
R6 ODT — — — — —
On-die termination,
resistor grounded
P11 Q0 1.5-V HSTL Class I AY13 AK14 N29 W35 Read data bus
M10 Q1 1.5-V HSTL Class I BD16 AL14 P30 T36 Read data bus
L11 Q2 1.5-V HSTL Class I BC16 AL15 G32 V36 Read data bus
K11 Q3 1.5-V HSTL Class I BB15 AL16 H31 U36 Read data bus
J10 Q4 1.5-V HSTL Class I BD13 AM14 H32 P37 Read data bus
F11 Q5 1.5-V HSTL Class I BC13 AN14 L30 P39 Read data bus
E11 Q6 1.5-V HSTL Class I BB14 AN15 L29 P38 Read data bus
C10 Q7 1.5-V HSTL Class I BA13 AR14 F32 P36 Read data bus
B11 Q8 1.5-V HSTL Class I AE18 AM16 M30 N38 Read data bus
B2 Q9 1.5-V HSTL Class I AE15 AR15 T31 N37 Read data bus
D3 Q10 1.5-V HSTL Class I AE16 AU13 R31 F36 Read data bus
E3 Q11 1.5-V HSTL Class I AG14 AT14 P31 G37 Read data bus
F2 Q12 1.5-V HSTL Class I AG15 AU14 U30 E36 Read data bus
G3 Q13 1.5-V HSTL Class I AJ14 AW13 T29 D37 Read data bus
K3 Q14 1.5-V HSTL Class I AH15 AV14 V31 B38 Read data bus
L2 Q15 1.5-V HSTL Class I AK15 AW14 W32 C37 Read data bus
N3 Q16 1.5-V HSTL Class I AF16 AT15 W31 A38 Read data bus
P3 Q17 1.5-V HSTL Class I AE17 AU15 Y32 B39 Read data bus
Table 2–26. FPGA2 QDRII+ Pin Assignments, Signal Names and Functions (Part 2 of 3)
Board
Reference
Schematic
Signal Name
I/O Standard
Stratix V GX FPGA Device Pin Number
Description
QDR2E QDR2F QDR2G QDR2H