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Altera FIR Compiler User Manual
Fir compiler user guide
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Altera FIR Compiler User Manual | 76 pages
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76
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Table of contents
Document Outline
FIR Compiler User Guide
Contents
1. About the FIR Compiler
Features
Release Information
Device Family Support
MegaCore Verification
Performance and Resource Utilization
Installation and Licensing
OpenCore Plus Evaluation
OpenCore Plus Time-Out Behavior
2. Getting Started
Design Flows
DSP Builder Flow
MegaWizard Plug-In Manager Flow
Parameterize the MegaCore Function
Generate the MegaCore Function
Simulate the Design
Compile the Design and Program a Device
3. Parameter Settings
Specifying the Coefficients
Using the FIR Compiler Coefficient Generator
Loading Coefficients from a File
Analyzing the Coefficients
Specify the Input and Output Specifications
Specify the Architecture Specification
Resource Estimates
Filter Design Tips
4. Functional Description
FIR Compiler
Number Systems and Fixed-Point Precision
Generating or Importing Coefficients
Structure Types
Interpolation and Decimation
Pipelining
Simulation Output
Avalon Streaming Interface
Avalon-ST Data Transfer Timing
Signals
Timing Diagrams
Reset and Global Clock Enable Operations
Single Rate Filter Timing Diagram
Interpolation Filter Timing Diagrams
Decimation Filter Timing Diagrams
Coefficient Reloading Timing Diagrams
Referenced Documents
A. FIR Compiler Supported Device Structures
Supported Device Structures
Support for HardCopy Series Devices
Compiling HardCopy Designs
Additional Information
Revision History
How to Contact Altera
Typographic Conventions
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