Altera FIR Compiler User Manual
Page 5
© May 2011
Altera Corporation
1. About the FIR Compiler
This document describes the Altera
®
FIR Compiler. The Altera FIR Compiler provides
a fully integrated finite impulse response (FIR) filter development environment
optimized for use with Altera FPGA devices.
You can use the Altera IP Toolbench interface with the Altera FIR Compiler to
implement a variety of filter architectures, including fully parallel, serial, or multibit
serial distributed arithmetic, and multicycle fixed/variable filters. The FIR Compiler
includes a coefficient generator.
Traditionally, designers have been forced to make a trade-off between the flexibility of
digital signal processors and the performance of ASICs and application-specific
standard product (ASSPs) digital signal processing (DSP) solutions. The Altera DSP
solution reduces the need for this trade-off by providing exceptional performance
combined with the flexibility of FPGAs.
shows a typical DSP system that uses Altera IP cores, including the FIR
Compiler and other DSP IP cores.
Many digital systems use signal filtering to remove unwanted noise, to provide
spectral shaping, or to perform signal detection or analysis. Two types of filters that
provide these functions are finite impulse response (FIR) filters and infinite impulse
response (IIR) filters. Typical filter applications include signal preconditioning, band
selection, and low-pass filtering.
In contrast to IIR filters, FIR filters have a linear phase and inherent stability. This
benefit makes FIR filters attractive enough to be designed into a large number of
systems. However, for a given frequency response, FIR filters are a higher order than
IIR filters, making FIR filters more computationally expensive.
Figure 1–1. Typical Modulator System
FEC
Reed Solomon
Encoder
Convolutional
Encoder
(Viterbi)
Constellation
Mapper
Outer Encoding Layer
Output
Data
Input
Data
NCO
Compiler
DAC
FIR Compiler
N
LPF
FIR Compiler
N
LPF
Convolutional
Interleaver
Inner Coding Layer
I
Q