Altera FIR Compiler - Manual (Page 17)

Chapter 2: Getting Started 2–3
MegaWizard Plug-In Manager Flow
© May 2011 Altera Corporation FIR Compiler User Guide
4. Verify that the device family is the same as you specified in the New Project
Wizard .
5. Select the top-level output file type for your design; the wizard supports VHDL
and Verilog HDL.
6. Specify the top level output file name for your MegaCore function variation and
click Next to launch IP Toolbench ( Figure 2–3 on page 2–4 ).
Parameterize the MegaCore Function
To parameterize your MegaCore function variation, perform the following steps:
1. Click Step 1: Parameterize in IP Toolbench to display the Parameterize - FIR
Compiler window. Use this interface to specify the required parameters for the
MegaCore function variation. For an example of how to set parameters for the FIR
Compiler MegaCore function, refer to
Chapter 3, Parameter Settings .
Figure 2–2. Selecting the MegaCore Function