Megacore verification, Performance and resource utilization – Altera FIR Compiler User Manual

Page 10

1–6

Chapter 1: About the FIR Compiler

MegaCore Verification

Altera Corporation

MegaCore Verification

Before releasing an updated version of the FIR Compiler, Altera runs a comprehensive
regression test to verify its quality and correctness.

All features and architectures are tested by sweeping all parameter options and
verifying that the simulation matches a master functional model.

Performance and Resource Utilization

This section shows typical expected performance for a FIR Compiler MegaCore
function with Cyclone III and Stratix IV devices. All figures are given for a FIR filter
with 97 taps, 8-bit input data, 14-bit coefficients, a target f

MAX

set to 1 GHz.

Cyclone III devices use combinational look-up tables (LUTs) and logic registers;
Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic
registers.

The resource and performance data was generated with the source ready signal
(

ast_source_ready

) always driven high, as described in

“Avalon Streaming

Interface” on page 4–13

Table 1–5

shows performance figures for Cyclone III devices:

Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 1 of 2)

Combinational

LUTs

Logic

Registers