Altera FIR Compiler - Manual (Page 35)

Chapter 3: Parameter Settings 3–11
Specify the Architecture Specification
© May 2011 Altera Corporation FIR Compiler User Guide
When adjusting the input and output specification, follow these tips:
■ Truncating from the MSB reduces logic resources more than saturation.
■ The Number of Input Channels option is useful for designs such as modulators
and demodulators, which have I and Q channels. If you are designing this type of
application, select 2 input channels. This tutorial uses the default settings.
Specify the Architecture Specification
You are now ready to select the architecture parameters from the lower half of the
Parameterize - FIR Compiler
page.
The FIR Compiler supports several filter structures, including:
■ Variable/Fixed coefficient: Multicycle
■ Distributed arithmetic: Fully Parallel Filter
■ Distributed arithmetic: Fully Serial Filter
■ Distributed arithmetic: Multibit Serial Filter
1 For maximum clock speed, select the Distributed Arithmetic: Fully Serial Filter
structure. (For Stratix, Stratix II, Stratix III, or Stratix IV devices, using smaller
memory resources for coefficient and data storage is faster than using larger memory
resources.) For maximum throughput, select the Distributed Arithmetic: Fully Parallel
structure.
When reloading coefficients, a multicycle variable FIR filter structure has a short
reloading time compared to a fixed FIR filter. Additionally, smaller memory blocks
have a shorter reloading time than larger memory blocks.
Table 3–3 describes the relative trade-offs for the different architecture options.
For more information about the filter architectures and how they operate, refer to
“FIR Compiler” on page 4–1 .
Table 3–3. Architecture Trade-Offs
Technology Option Area Speed (Data Throughput)
Distributed
arithmetic Fully parallel Large area Creates a fast filter: 140 to over 300 MSPS throughput with
pipelining in Stratix II devices.
Distributed
arithmetic Fully serial Small area Requires multiple clock cycles for a single computation.
Distributed
arithmetic Multibit
serial Medium area Uses several serial units to increase throughput.This results
in greater throughput than fully serial, but less throughput
than fully parallel.
DSP block
multiplier Multicycle Area depends on the number
of calculation cycles selected
(area increases as the number
of calculation cycles increases) Data throughput increases as the number of calculation
cycles decreases. This architecture takes advantage of
Stratix, Stratix II, Stratix III, or Stratix IV DSP Blocks, and
Cyclone II Multipliers.
Available
option for all
architectures Pipelining Creates a higher performance
filter with an area increase. Increases throughput with additional latency and size
increase.