Altera FIR Compiler - Manual (Page 57)

Chapter 4: Functional Description 4–15
Avalon Streaming Interface
© May 2011 Altera Corporation FIR Compiler User Guide
The sink indicates to the source that it is ready for an active cycle by asserting the
ready signal for a single clock cycle. Cycles during which the sink is ready for data
are called ready cycles. During a ready cycle, the source may assert valid and provide
data to the sink. If it has no data to send, it deasserts valid and can drive data to any
value.
When READY_LATENCY=0, data is transferred only when ready and valid are
asserted on the same cycle. In this mode of operation, the source data does not need to
receive the sink’s
ready signal before it begins sending valid data. The source
provides the data and asserts valid whenever it can and waits for the sink to capture
the data and assert ready . The sink only captures input data from the source when
ready and valid are both asserted.
Figure 4–12 illustrates the data transfer timing.
The source provides data and asserts valid on cycle 1, even though the sink is not
ready. The source waits until cycle 2, when the sink does assert ready , before moving
onto the next data cycle. In cycle 3, the source drives data on the same cycle and
because the sink is ready to receive it, the transfer occurs immediately. In cycle 4, the
sink asserts
ready , but the source does not drive valid data.
Packet Data Transfers
A beat is defined as the transfer of one unit of data between a source and sink
interface. This unit of data may consist of one or more symbols and makes it is
possible to support modules that convey more than one piece of information about
each valid cycle. Packet data transfers are used for multichannel transfers. Two
additional signals (
startofpacket and endofpacket ) are defined to implement
the packet transfer.
Figure 4–13 shows an example where the channel signal shows to which channel the
data sample belongs.
1
The channel input signal is not used in the FIR Compiler interface.
Figure 4–12. Avalon-ST Interface Timing with READY_LATENCY=0
D
o
D
1
D
2
0 1 2 3 5 6 7 8 4
clk
ready
valid
error
data
00 00 00 00
D
2
Figure 4–13. Packet Data Transfer
0 1 2 3
00 00 00 00
D
0
D
1 D 2
D
3
1 2 3 4 5 6 7
clk
ready
valid
startofpacket
endofpacket
channel[1:0]
data
error[1:0]