Table 3–7, Note 1) – Altera FIR Compiler User Manual
Page 38
3–14
Chapter 3: Parameter Settings
Specify the Architecture Specification
© May 2011
Altera Corporation
Coefficient Reload
If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Pipeline Level
Creates a higher performance filter with a resource usage increase.
Use Single Clock
Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the
coef_clk_in
and
clk
signals together.
Note to
(1) The bit width of input data should divide evenly by the number of serial units and result of division must be greater than or equal to four.
Table 3–7. Fully Parallel Filter Architecture
Parameters
Description
Data Storage
Specifies the device resources used for data storage. You can select Logic Cells or Auto. If you
select Auto, the Quartus II software may store data in logic cells or memory, depending on the
resources in the selected device, the size of the data storage, and the number of input channels.
Coefficient Storage
Specifies the device resources used for coefficient storage. You can select Logic Cells, M512,
M4K, MLAB, M9K, or Auto. If you select Auto, the Quartus II software automatically selects the
most appropriate memory block size for the selected device.
The option list changes depending on which device you select. Selecting embedded memory
reduces logic cell usage and may increase the speed of the filter.
Force Non-Symmetric
Structure
If you want to create a design that uses both symmetric and non-symmetric coefficients, turn on
this option. Non-symmetric architectures may use more resources.
This option is available when coefficients are stored in the embedded memory.
Coefficient Reload
If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Pipeline Level
Creates a higher performance filter with a resource usage increase.
Use Single Clock
Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the
coef_clk_in
and
clk
signals together.
Note to
:
(1) When input data is unsigned, the input data bit width should be greater than or equal to one. When input data is signed, the input data bit width
should be greater than or equal to two.
Table 3–6. Multibit Serial Filter Architecture (Part 2 of 2)
(Note 1)
Parameters
Description