Altera FIR Compiler - Manual (Page 53)

Chapter 4: Functional Description 4–11
FIR Compiler
© May 2011 Altera Corporation FIR Compiler User Guide
Availability of Interpolation and Decimation Filters
Interpolation and decimation filters are available for all architectures:
■ Parallel distributed arithmetic
■ Serial distributed arithmetic
■ Multibit serial distributed arithmetic
■ Multicycle variable structures
All architecture configuration options are available for interpolation and decimation
filters, including:
■ User configuration of data storage type (memory or logic cells)
■ User configuration of coefficient storage type (memory or logic cells)
■ Multichannel capability
■ Multiple coefficient set capability
Family-Specific Features
Stratix IV, Stratix III and Stratix II filters implement ternary adder structures in all
architectures:
■ Fully parallel distributed arithmetic
■ Fully serial distributed arithmetic
■ Multibit serial distributed arithmetic
■ Multicycle variable
Figure 4–10. Decimation Filter Structure
P(0)
P(1)
P(2)
P(N-1)
output
input
input
N Channel
N Coefficient Set
Single Rate FIR Filter
Control
Circuitry
Accumulator
input
LPF
output
N
output