Altera FIR Compiler - Manual (Page 50)

4–8 Chapter 4: Functional Description
FIR Compiler
FIR Compiler User Guide © May 2011 Altera Corporation
Figure 4–6 shows the area/speed “trade-off” of fixed FIR filters.
Two serial filters operating in parallel compute the result at twice the rate of a single
serial filter. Three serial filters operate at triple the speed; four operate at four times
the speed. For example, a 16-bit serial FIR filter requires 16 clock cycles to complete a
single FIR calculation. A multibit serial FIR filter with two serial structures takes only
eight clock cycles to compute the result. Using four serial structures, only four clock
cycles are required to perform the computation. Three serial structures cannot be used
for a 16-bit serial structure, however, because 16 does not divide evenly by three.
Multichannel Structures
When designing DSP systems, you may need to generate two FIR filters that have the
same coefficients. If high speed is not required, your design can share one filter, which
uses fewer resources than two individual filters. For example, a two-channel parallel
filter requires two clock cycles to calculate two outputs. The resulting hardware
would need to run at twice the data rate of an individual filter.
1 To minimize the number of logic elements, use a distributed serial arithmetic
architecture, multiple channels, and memory blocks for data and coefficient storage.
Interpolation and Decimation
You can use the FIR Compiler to interpolate or decimate a signal. Interpolation
generates extra points in between the original samples; decimation removes
redundant data points. Both operations change the effective sample rate of a signal.
1 The outputs from interpolating and decimating filters that have the same input data
are likely to be different. This difference is because changing the delay between the
reset signal and the first non-zero input data sample may make the input sample go
down a different path of the polyphase filter. This means that the input data is
multiplied by a different set of coefficients and the filter results are different.
Figure 4–6. Fixed FIR Filters: Area Vs. Throughput
Multi-Bit
Serial
Throughput
Area
Serial
Parallel
With Extended
Pipelining
With Extended
Pipelining
With Extended
Pipelining