Altera FIR Compiler - Manual (Page 15)

© May 2011 Altera Corporation FIR Compiler User Guide
2. Getting Started
Design Flows
The FIR Compiler MegaCore ® function supports the following design flows:
■ DSP Builder : Use this flow if you want to create a DSP Builder model that
includes a FIR Compiler MegaCore function variation.
■ MegaWizard™ Plug-In Manager : Use this flow if you would like to create a FIR
Compiler MegaCore function variation that you can instantiate manually in your
design.
This chapter describes how you can use a FIR Compiler MegaCore function in either
of these flows. The parameterization is the same in each flow and is described in
Chapter 3, Parameter Settings .
After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.
DSP Builder Flow
Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an algorithm-
friendly development environment.
DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB
® and Simulink ® system-level design tools
with Altera Quartus ® II software and third-party synthesis and simulation tools. You
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system level specifications and perform simulation.
In DSP Builder, a Simulink symbol for the FIR Compiler appears in the MegaCore
Functions
library of the Altera DSP Builder Blockset in the Simulink library browser.
You can use the FIR Compiler in the MATLAB/Simulink environment by performing
the following steps:
1. Create a new Simulink model.
2. Select the FIR Compiler block from the MegaCore Functions library in the
Simulink Library Browser, add it to your model, and give the block a unique
name.
3. Double-click the FIR Compiler block in your model to display IP Toolbench and
click Step 1: Parameterize to parameterize a FIR Compiler MegaCore function
variation. For an example of how to set parameters for the
FIR Compiler block,
refer to Chapter 3, Parameter Settings .
4. Click Step 2: Generate in IP Toolbench to generate your FIR Compiler MegaCore
function variation. For information about the generated files, refer to Table 2–1 on
page 2–6 .
5. Connect your FIR Compiler MegaCore function variation block to the other
blocks in your model.